In a wireless communication system, a transmitted radio wave may arrive at a receiving apparatus through two or more paths. The receiving apparatus receives two or more incoming waves that have arrived through the two or more paths, at timings depending on their respective paths. This may cause intersymbol interference. Intersymbol interference means that adjacent symbols are affected by each other. Since communication quality is degraded by intersymbol interference, a receiving apparatus generally uses an equalizer for minimizing intersymbol interference. An equalizer that performs equalization in a time domain determines the position of each incoming wave in a received signal, that is, the timing of each incoming wave, and determines a preceding wave timing that is the arrival timing of a leading wave that is a wave arriving at the earliest time, and a most-delayed wave timing that is a timing of a most-delayed wave that is a wave arriving at the latest time. Then, the equalizer estimates a length between the preceding wave timing and the most-delayed wave timing, that is the spread of delay, and sets a timing of performing equalization and a tap length using the spread of delay. When the receiving apparatus can accurately estimate the spread of delay, it can appropriately set the timing of performing equalization and the tap length, and as a result, can improve the communication quality. For this reason, accurately estimating the timings of incoming waves has been a certain challenge.
Conventional techniques for estimating the timings of incoming waves include a technique described in Patent Literature 1. In a communication system in which a known sequence such as a synchronization symbol string or a training signal is contained in a frame, a synchronization detection circuit described in Patent Literature 1 delays a received signal symbol by symbol using a shift register, performs a convolution operation on an input signal and the known sequence, that is, an operation to obtain the cross-correlation between the input signal and the known sequence, and successively outputs a correlation value resulting from this operation. The synchronization detection circuit described in Patent Literature 1 detects a position at which the correlation value is largest, and sets the detected position as a synchronization timing, that is, the position of a main wave. The synchronization detection circuit described in Patent Literature 1 estimates a delay profile by regarding, as a delayed wave, one whose correlation value is relatively large among the calculated correlation values other than the main wave.